To use an ODB++ netlist, create or edit a board in XJDeveloper, and check the “ODB++ Project” radio button. Finally browse to the ODB++ file or directory and click OK.

Once XJDeveloper has loaded the netlist, you will be able to view circuit elements in the viewer. This feature is available throughout XJDeveloper. For example you can right-click on a net and choose “Show in Layout Viewer”. The Layout Viewer will be opened and the net will be highlighted.

Errors in the connection test are displayed as hyperlinks (in both XJDeveloper and XJRunner). Clicking the links will display the nets in the Layout Viewer:

Future information on the Layout Viewer can be found in the help files.

Device Library

The device library contains descriptions for passive and test devices. Instead of manually writing the definitions of the devices yourself, or going to the XJTAG website to get them, they are now available directly from within XJDeveloper.

Updates

We are continuously developing and improving this library. Every now and then XJDeveloper will tell you that an new version of the library is available, and it can download and install it automatically if required. This means that you will always have access to new device definitions as XJTAG develop then, as well as the the latest versions of existing definitions.
When you open a project, XJDeveloper will check the definitions used in the project against those in the library. If there are any updated versions available, you will be able to update the definitions used in your project.

Using the library

Everywhere you categorise devices in XJDeveloper, you can now browse the library and select the definition you want. We have also gone one step further, and XJDeveloper will search the library for matching definitions for you automatically.

Suggested Categorisation

Whenever you categorise a device as test or passive, the list of definitions available will now include any matches from the library. XJDeveloper uses BOM information as well as inspecting your netlist to determine possible matches.

You can also get any suggested matches from the library for all the devices on the board by pressing the “Suggest” button on the Categorise Devices screen. This means that with one click you can automatically categorise a large proportion of the devices in the circuit!

Logic devices are categorised on the Categorise Devices screen, much like test, passive, unfitted and ignore devices. The Categorise As section lists the recently used definitions so similar devices can be quickly defined.

When you categorise a device as Logic the following dialog appears:

• Search File
  Select a file to search for a logic definition. The list of files will always include the XJTAG logic library. If you have your own logic definitions then you can search them here.
• Search Name and Search Description
  The XJTAG logic library contains over 150 different types of logic (and is still growing!). To help you find the required definition you can enter part of the name or a description of the device (e.g. “Inverter”). The list of definitions shown will shrink as you type to contain only definitions that match.
• Footprints
  A device may be available in several footprints. Each entry in the Footprints column contains a drop-down with the set of footprints that definition covers. The Summary shows the details for the selected footprint, and the Show Details… button will display the full details of the definition to make sure you select the correct one.

Types of reports you can generate

• Analysis by Circuit Element
  This report contains statistics for elements in the circuit. These can either be the entire circuit or for groups of elements such as boards, devices or nets. It can also provide detailed test coverage for each pin.
• Analysis by Coverage Type
  This report produces board level lists of individual pins according to whether or not they are covered for specific types of test coverage.
• Test Point Reduction
  Having test points on nets where good test coverage can be achieved with XJTAG is not necessary and uses up board space. This report lists these nets and suggests elimination of the test points where appropriate.
• Test Point Suggestion
  It is possible that test coverage on some nets could be improved by adding a test point. This report suggests nets where the designer might consider adding them.

Generating DFT Reports

DFT reports can be generated without having to go to the DFT screen: the Reports wizard can be launched from the Reports button in the Tools menu from anywhere in XJDeveloper. If you are on the DFT screen you can also launch the Reports wizard by clicking the corresponding button at the bottom of the circuit elements list.

Note that the filter options set on the Reports wizard are independent from the ones on the DFT Analysis screen; any filter options used on the DFT Analysis screen to narrow down data have no effect on the generated reports.

• There is a new improved circuit elements list which shows the element’s name along with all the calculated test coverage in adjacent sortable columns, that can be shown or hidden, so you can easily explore the results of the DFT analysis.

• The DFT Analysis screen features new improved charts with a modern and professional look; figures, percentages and graphical representation of the DFT analysis data are now displayed in a concise form, so with one glance you can see an overview of the test coverage of your circuit, or of individual circuit elements or groups of elements.

• There are improved filtering options to enable you to narrow down the display to the data of interest and focus on untested sections of your circuit.

The above features are displayed on “dockable” panels allowing you to set up your own preferred configuration of the DFT Analysis screen for maximum efficiency.

We decided a long time ago that XJTAG should support “simple” logic devices in such a way that the logic is handled transparently when it comes to XJEase code, thus allowing the Test Device code to remain device-centric. We also decided that the built-in connection test had to support logic devices to the same extent. The work was on-going behind the scenes here at XJTAG for some time, and is a major part of the version 2.4 release.

So, in previous versions of XJEase if you had a memory chip with a data bus which was accessed through a buffer, you had to modify the chip’s device file so that the data bus pins were actually the buffer inputs rather than the chip’s own data pins. This will still work… but it’s no longer necessary – XJTAG will now realise (for example) that if you want to write to a particular pin on that data bus then it means setting the appropriate buffer direction, enable and input pins, and that if you later want to read the pin, XJTAG will stop driving the buffer, change the buffer’s direction and then read the value through from the memory.

Limitations

No Logic with State

XJTAG  version 2.4 does not support logic with state.  This does not only apply to individual gates – we also do not support the situation where blocks are combined to store state, for example constructing a flip-flop from NAND gates. XJTAG will attempt to spot such situations and object to them… but if you manage to be more cunning than our compile-time state detection algorithms it still won’t work correctly at runtime!

Wind-up of logic blocks

When you make SET statements in XJEase you are asking XJTAG to put the circuit in a state and leave it that way until told to do otherwise.  And with logic that gets complicated. For example, imagine a logic device with 2 outputs and a truth table set up such that they can’t both output a 1 (ie valid output states are 00, 01, 10 only). The user makes a SET statement that sets the first one high. Fine so far. But then later the user SETs the 2nd one high. Now we have a dilemma. Should we refuse? Or should we set the first one back low in order to comply with the 2nd request? The problem would be worse if there were 3 outputs and any two could be high – which one should we set back low in order to set the 3rd one high?

Because we can’t know what the user actually wants, we will stop and show an error if this situation arises. In general that’s easy for you to get around because having SET a value on a pin, you can always SET a different value on it – so you can SET the first pin back low once you’re done with it (or as you SET the 2nd one high)

If the situation gets far too complicated for you to work out what is causing the conflict, which may mean the SET causing the problem was made in some other test a long way from where you are, then we do have a (slightly drastic) get-out, which is to make a  SAFE; statement in your code. This resets all pins (and logic blocks) in the circuit to their default state.

We hope that the new logic features in XJTAG are useful to you – please give us feedback if you feel you have a situation that we should support and don’t, or if you have further suggestions as to how we can improve the products.

When you first test a new circuit board that doesn’t work this diagnostics test can give you confidence that your XJlink2 hardware is working correctly. The test takes a few minutes to run but tests all of the internal features of the XJlink2 in detail. The test includes checks on:

• all of the connector signal driver transistors
• all of the signal input buffers
• the connector power supplies
• the internal signal communication buses
• the internal clock sources
• and the integrity of the internal program.
• the push-button
• and the LEDs.

You can optionally use a loop-back connector ( pin1 to pin11, pin2 to pin 12 etc) to provide enhanced testing of the connector itself.

If you think you might have damaged your XJlink2 then just run the self test. If a test fails please copy the entire report along with your serial number to support@xjtag.com so that we can help you.

The diagnostics feature is an excellent way to confirm that the XJLink2 is working correctly.

Test jig integration

Some of our customers built the original XJLink into custom test rigs. The XJLink2 goes further in supporting this kind of customisation: the button signal and the LED signals can be replicated on the 20-way connector. In the Pinmap settings for your project just enable the advanced option and you are able to assign these signals to spare I/O pins. You are then able to wire this up however you like. For example, you may put a button on the front panel of a test jig and use that to start the tests. In addition, the LED signals can be replicated to the front panel of the test jig or to an alarm if required. If you have an externally controllable PSU you may connect the Yellow ( running ) light so that only when a test has started will the PSU be turned on. Once the test is stopped the PSU will automatically be turned off.