We understand that sometimes (for your own sanity if nothing else) you need to test that your test equipment is working. For this reason, it is possible to run a health-check on XJLink2 hardware (and XJLink2-based hardware) using the self-test feature available in the XJLink Manager. The self test can be run with or without a loopback connector but should never be run with the XJLink connected to test hardware. […]
Alongside other improvements to the XJRunner test setup, XJTAG v3.5 has a new interface to specify bus access from the test system using the XJRunner Setup screen. When you edit a test there is now a Bus Access tab on the dialog, which allows full control of which pins are used to read and/or write from a bus during the test. […]
We have launched a new website today. As a result, existing logins for support and downloads will no longer work. Customers will need to create a new account, by clicking Sign in at the top and then clicking Register. You will immediately be able to submit support enquiries. Assuming you're in maintenance, XJTAG will activate [...]
With the new XJEase Library we have made some fairly extensive changes to reduce code duplication, to improve test coverage, and ease of use. If you have used additional code files from the XJEase library to create your own test scripts you may find that updating to the new versions of these files causes errors in your project. Below are the common errors you might see and how to fix them. […]
Recently one of our newer customers started on their first solo board setup. They had previously seen XJTAG demonstrated and had also had their initial board setup done by an XJTAG engineer. When they came to setting a board up for themselves they tried to follow the path that the XJTAG engineer had talked them through – […]
We have been starting to see questions about support for DDR4 SDRAM devices, which are gradually becoming available. We have published a guide to using JTAG to test DDR4 memory on the XJTAG website. It contains a link to slides used at a recent presentation on the subject. Support for DDR4 devices will be coming soon [...]
When using JTAG with a Device Under Test (DUT) connected to a bed-of-nails test fixture, often little attention is paid to the way the JTAG signals are wired. This article (published in SMT magazine last year) gives a helpful explanation of why it is important to get this right, and gives tips for best practice.