Archive for the ‘XJDeveloper’ Category
Create your own links to Layout Viewer from XJEase
9 January, 2012
From version 2.6.2 onwards XJEase supports the printing of device, pin and net links which launch and get highlighted in Layout Viewer from XJRunner and XJDeveloper (provided there is an ODB++ netlist available for the board). Read the rest of this entry »
Layout Viewer
19 December, 2011
If your project uses an ODB++ netlist, then you can take advantage of the Layout Viewer in both XJDeveloper and XJRunner. Layout Viewer uses the layout information in the netlist to allow you to visualise the physical location of components, pins and nets on a board. This is especially useful for visualising errors from the connection test to guide you towards the most likely location of a fault on a board. Read the rest of this entry »
Device Library
5 December, 2011
Version 2.6 of XJDeveloper has two exciting new features that make developing your projects easier – a library of definitions for devices and a “suggest categorisation” feature. Read the rest of this entry »
XJTAG Logic Library
20 December, 2010
From version 2.4 XJDeveloper and XJRunner support logic devices. A library of definitions for common logic devices is shipped with XJDeveloper. This post details this feature. Read the rest of this entry »
Categorising Devices as Logic in XJDeveloper
6 December, 2010
This post outlines how to categorise a device as a logic device in XJDeveloper and explains some of the useful features. Read the rest of this entry »
Design for Test Analysis in XJDeveloper 2.4 – Part 2
22 November, 2010
This post introduces the new DFT reports which are generated from the DFT analysis data. This is a feature introduced in XJTAG version 2.4.
Read the rest of this entry »
Clearing Altera Cyclone III Devices
8 November, 2010
In the XJTAG application note “Working with configured Xilinx and Altera devices” the point is made that the way to get the best test coverage is to test with blank devices.
Blanking a device has its own challenges – Read the rest of this entry »
Design for Test Analysis in XJDeveloper 2.4 – Part 1
25 October, 2010
The DFT Analysis screen in XJTAG version 2.4 has been completely redesigned to allow you to assess the test coverage of your circuit design more easily and in a more efficient way. This post highlights the most important new features. Read the rest of this entry »
Categorising devices in XJDeveloper – 10 rules of thumb
11 October, 2010
We asked one of the guys in-house who works with XJDeveloper most of the time to give some tips from his experience of setting up projects, and here is what he came up with: Read the rest of this entry »
Using CONNECT vs PULL in PDD files
27 September, 2010
Why use CONNECT not PULL for low-value pull resistors? When a resistor is specified as a pull resistor the XJTAG system will expect two things: Read the rest of this entry »