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Layout Viewer

If your project uses an ODB++ netlist, then you can take advantage of the Layout Viewer in both XJDeveloper and XJRunner. Layout Viewer uses the layout information in the netlist to allow you to visualise the physical location of components, pins and nets on a board. This is especially useful for visualising errors from the connection test to guide you towards the most likely location of a fault on a board. […]

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Device Library

Version 2.6 of XJDeveloper has two exciting new features that make developing your projects easier – a library of definitions for devices and a “suggest categorisation” feature. […]

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XJTAG Logic Library

From version 2.4 XJDeveloper and XJRunner support logic devices. A library of definitions for common logic devices is shipped with XJDeveloper. This post details this feature. […]

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Categorising Devices as Logic in XJDeveloper

This post outlines how to categorise a device as a logic device in XJDeveloper and explains some of the useful features. […]

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Design for Test Analysis in XJDeveloper 2.4 – Part 2

This post introduces the new DFT reports which are generated from the DFT analysis data. This is a feature introduced in XJTAG version 2.4. […]

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Clearing Altera Cyclone III Devices

In the XJTAG application note “Working with configured Xilinx and Altera devices” the point is made that the way to get the best test coverage is to test with blank devices. Blanking a device has its own challenges – […]

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Design for Test Analysis in XJDeveloper 2.4 – Part 1

The DFT Analysis screen in XJTAG version 2.4 has been completely redesigned to allow you to assess the test coverage of your circuit design more easily and in a more efficient way. This post highlights the most important new features. […]

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Categorising devices in XJDeveloper – 10 rules of thumb

We asked one of the guys in-house who works with XJDeveloper most of the time to give some tips from his experience of setting up projects, and here is what he came up with: […]

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Using CONNECT vs PULL in PDD files

Why use CONNECT not PULL for low-value pull resistors? When a resistor is specified as a pull resistor the XJTAG system will expect two things: […]

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Logic in XJTAG – capabilities and limitations

We see a lot of logic components used on boards that come through our office. Most often we see buffers, bus transceivers and devices of that nature, but also plenty of the usual discrete logic chips – simple gates, decoders, encoders etc. […]

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