Creating SVF files to program Xilinx FPGAs has historically been accomplished using iMPACT, installed as part of Xilinx’s ISE Design Suite.  With Xilinx’s most recent FPGAs this is no longer possible and instead their new tool, Vivado, must be used.

The following instructions guide you through this process and assume version 2016.1 or later of Vivado.

All the tcl commands below should be used either within the Vivado GUI, or within a Vivado Tcl Shell.  For earlier versions of Vivado an alternative approach is required, so please contact us if you need further assistance with this.

Having generated the bitstream for the required FPGA image, it’s then necessary to open the hardware tool and connect to the hardware server using the tcl commands:

open_hw
connect_hw_server -quiet

At this point there are two ways to proceed, one requires the board to be connected to the PC via a programming cable that works with Vivado, and the second requires no external hardware whatsoever.  For simplicity, this blog article will concentrate on the second approach.

Vivado must be told what device(s) to include in its SVF file using a combination of the following three tcl commands:

create_hw_target my_svf_target
open_hw_target 
[get_hw_targets -regexp .*/my_svf_target]
set device0 [create_hw_device -part partnum]

The first of these creates a new SVF target.  If a target with this name has already been created then you will either need to use a different name for this new target, or delete the old target using the tcl command:

delete_hw_target [get_hw_targets -regexp .*/my_svf_target]

The second of the commands above opens up this new SVF target that’s been created.  If this command fails then it’s most likely because another target is already open.  You can resolve this by closing the open target using the following tcl command before continuing:

close_hw_target

The final command of the 3 above adds a new part to the SVF target, and stores a reference to this part in the variable device0.  The text ‘partnum’ should be changed to match the part number of the target device to be programmed, excluding the footprint section from the part number.   For example if the device is a xcku040-fbva676-1 then this would be:

set device0 [create_hw_device -part xcku040]

If you’re not sure what value to use, run the following command with the Vivado project open and it will tell you:

puts [get_property device [get_property part [current_project]]]

Even if there are other devices on the JTAG chain, it is not necessary to specify these when creating an SVF file to use with XJTAG, because XJTAG will automatically handle the other devices present.

At this point the bit file to program into the FPGA must be specified. This can be done either via the Vivado GUI or using tcl.  To use the GUI, click on the device that has appeared in the Hardware section, and then in the Hardware Device Properties section select the General tab and set the Programming file to the required bit file.  Alternatively, the same can be achieved using the following tcl command, substituting filename.bit for the name of the bit file:

set_property PROGRAM.FILE {filename.bit} $device0

The filename can be either a path relative to the current working directory, returned using the pwd command, or an absolute path.

Before creating the SVF file on disk there is one more tcl command that is required:

set_param xicom.config_chunk_size 0

Running this command ensures that the generated SVF file is compatible with a JTAG chain that also includes other devices. Without this, the XJTAG RUNSVF function will most likely fail when there are other devices on the JTAG chain.

At this point, the SVF file can be generated using the tcl command:

program_hw_devices -force -svf_file {filename.svf} $device0

As with the set_property command above, the filename can be either a path relative to the current working directory, returned using the pwd command, or an absolute path.

An SVF file has now been generated that can be used with XJTAG via the RUNSVF function.  With this function, the ‘devices’ parameter should just specify the device reference of the FPGA for which the SVF file was generated.

To minimise the time taken to run the SVF file, it is sensible to compress the bitstream used to generate it.  This can be achieved using the GUI, via tcl, or by adding a single line to an xdc constraints file.  Editing the constraints file is by far the easiest, achieved by adding the line:

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

If you prefer to use the GUI then you must first open the Implemented Design before opening the Bitstream Settings window, found under the Program and Debug section in the Flow Navigator.  Click on the ‘Configure additional bitstream settings’ link towards the top of the window and then change the ‘Enable Bitstream Compression’ setting to TRUE. When subsequently saving the project you will be prompted to specify which file to add the corresponding constraint to.

Having changed this setting, it is then necessary to regenerate the bitstream before going through the steps above to generate the SVF file using this new, compressed, bitstream.

More information about generating SVF files and using Vivado can be found in the Xilinx User Guide UG908 ‘Vivado Design Suite User Guide – Programming and Debugging’.

When using SVF files to program Zynq-7000 devices, the SVF files generated do not include all of the required JTAG scans to guarantee the programming will always work.  Therefore, if you are trying to program a Zynq device using an SVF file then please contact us and we will help you update your XJTAG project accordingly.