XJTAG 3.12 expanded the capability of the Signal Integrity Analysis in XJTAG tools, adding the ability to suggest certain causes of error. This post continues from the previous post on this subject, and describes further errors that XJTAG tries to identify. […]
Some devices need more than a standard Test Reset sequence to enter the state when they behave as described in their BSDL file and boundary scan can run. Infineon’s Aurix TriCore TC3xx microcontroller family is one such group. […]
The blog article ‘Debugging Connection Test – part 1 (Updated)’ discusses how to use ‘Debug Connection Test’ to identify a missing disable value. However, if a disable value is set to the wrong value, i.e. low rather than high, then it could prevent the Debug Connection Test from running at all. In this case, XJDeveloper’s Analyser screen can be used to help locate the issue. […]
Creating SVF files to program Xilinx FPGAs has historically been accomplished using iMPACT, installed as part of Xilinx’s ISE Design Suite. With Xilinx’s most recent FPGAs this is no longer possible and instead their new tool, Vivado, must be used. The following instructions guide you through this process and assume version 2016.1 or later of Vivado. […]
When using JTAG with a Device Under Test (DUT) connected to a bed-of-nails test fixture, often little attention is paid to the way the JTAG signals are wired. This article (published in SMT magazine last year) gives a helpful explanation of why it is important to get this right, and gives tips for best practice.
Texas Instruments’ OMAP processors are becoming more and more popular. We have seen quite a few come through the office recently. The good news is that the OMAP processors do support boundary scan testing. […]
The traditional technique for debugging printed circuit boards is to “observe” the state using oscilloscopes or multi-meters and deduce a fault. This method actually suppresses a very powerful engineering instinct that would help us a lot if we could only give it a better chance. […]