This blog article is the final part of the three part series detailing the new Revisions feature in XJDeveloper 3.10. This article looks under the hood at how the device matching algorithm works. […]
When using JTAG with a Device Under Test (DUT) connected to a bed-of-nails test fixture, often little attention is paid to the way the JTAG signals are wired. This article (published in SMT magazine last year) gives a helpful explanation of why it is important to get this right, and gives tips for best practice.
Texas Instruments’ OMAP processors are becoming more and more popular. We have seen quite a few come through the office recently. The good news is that the OMAP processors do support boundary scan testing. […]
One of the exciting new features of XJLink2 is the ability to measure a number of voltages. Via the 20-way XJlink2 connector you can measure up to 18 different voltages. This means supply rail voltages can be measured before (and during) JTAG testing, and analogue measurements are now simple to make during your tests. [...]
Many of us have been designing electronics for years and haven’t really considered pull up and down resistor values. We just use the same old values like 10K. With some new silicon the leakage currents are higher than we have been used too. This means the pull resistors might not being doing the task we [...]