Understanding the connection test output

When Connection Test finds an error on a board it tries to ascertain what the problem is. This may involve carrying out additional checks, to try to eliminate noise on a floating net or cross-talk as a cause of the behaviour. If the fault appears to be genuine then the Connection Test reports the error.

On seeing a fault, most people’s first reaction is to want more information. So the first step for most people is to re-run the connection test with the debug level turned up, in order to see the output.
To do this, on the Run Tests screen in XJDeveloper or the main screen in XJRunner, look at the list of tests on the right (in XJRunner you need the ‘enhanced testing’ privilege to see this). At the bottom, there is a button marked “Options…”. Click on this to see a pop-up with various
options. The last tab of those options is marked ‘Connection Test’ and allows you to vary the output level. Set that debug level to “All”. Now re-run the connection test. Now it will show you a large amount of data for each fault.

For example (taken from the XJDemo board):


Error: Short found between nets: DIL10, DIL11.

Net DIL10 contains:
R39.2
JP6.20
CN3.11
IC3.18(IO18)
IC5.24

Net DIL11 contains:
CN3.12
R40.2
JP6.18
IC3.19(IO19)
IC5.25

      DIL10	 DIL11
      W     R    W     R
0     -     0    -     0
1     -     0    -     0
2     -     0    -     0
3     -     0    -     0
4     0     0    0     0
5     1     1    1     1
6     0     0    0     0
7     1     1    1     1
8     0     0    -     0    *
9     1     1    -     1    *
10    0     0    -     0    *
11    1     1    -     1    *
12    0     0    0     0
13    1     1    1     1
14    0     0    0     0
15    1     1    1     1
16    0     0    0     0
17    1     1    1     1
18    0     0    0     0
19    1     1    1     1
20    -     0    0     0    *
21    -     1    1     1    *
22    -     0    0     0    *
23    -     1    1     1    *
24    -     0    -     0
25    -     0    -     0
26    -     0    -     0
27    -     0    -     0
28    0     0    0     0
29    1     1    1     1
30    0     0    0     0
31    1     1    1     1
32    -     0    -     0
33    -     0    -     0

The first bit is easily understandable – XJTAG thinks there is a short between the two nets listed. The pins on each net are then listed because often looking at the lists of pins on the two nets will show that some adjacent pins are involved, which raises suspicions of a solder short  between pads on the board. You can also see if any test points or components such as resistors are on the nets should you wish to confirm the fault with a probe or multimeter.

Underneath that is the data.
This is the write (W) and read (R) information XJTAG has stored during the test. Depending on the type of fault this may be the value read on a net or value from an individual pin. For example with an open on the net it will display pins information, to let you see which pin doesn’t follow the rest of the net. In this case, because the error is a short circuit, the data is for nets. Down the left hand side are test numbers, and then the read and write values for each of the nets.

Marked tests (*)

For certain types of fault XJTAG marks (in groups of 4) tests where it considers the error to manifest itself by putting a * character to the right. For some faults it does not make sense to do this (stuck-at faults would be pretty boring) but where it is relevant the *s are shown.
In the above example, each set of *s shows a place where one of the nets is not being driven, yet it is picking up the value of the other net.

Update: More recent versions of XJTAG output a prettier HTML table for the error details. In this case, the marked tests are coloured blue.

Undetermined faults

There are two error messages which indicate that XJTAG found something wrong but that it is unable to diagnose what the problem is. These error messages look like:

Error on net XXX: Undetermined error (possible open pin)

or

Error on net XXX: Either it is shorted to another net
or a non-JTAG pin is also driving the net.

Sometimes these errors occur because the circuit is more complicated than XJTAG has been told (eg logic devices or buffers (uni-directional devices) have been represented as simple connections) or because there are multiple interacting errors on the board which make it difficult to determine each one individually. Unfortunately XJTAG is going to have to pass the investigation of this one over to you. A good place to start is by checking whether this net can be driven by anything
else, and if so, whether that device has its disable values set correctly to prevent it driving the net during the connection test. XJAnalyser (if you have the licence) is also an extremely useful
way to investigate this kind of fault further.