We all pay close attention to the termination of high speed signals, especially clock signals. However in many of the designs I see this doesn’t seem to have happened for the JTAG clock signal TCK. But TCK is a clock signal just like any other clock signal.
Some people believe that because JTAG is only for test it doesn’t matter. Other people think that you can just reduce the clock frequency during testing to solve problems. But terminating the TCK signal correctly really does matter! High speed JTAG interfaces have a need to have fast rise and fall times to ensure good signal quality. It is these fast edges that cause problems with poorly terminated boards. The usual problem is a reflection causing an extra clock pulse. If you want to try and have a look at this on a scope you will need a fast scope (500MHz or greater bandwidth), a good probe and a very short ground connection (<1 inch). Turn up the timebase and look at the rising edge of the clock. In a good system the edge will rise continuously and have no dips on the way up to the logic 1 level. A poorly terminated system will have a rising edge and then a dip and continue rising again. This dip can cause an extra clock edge. JTAG interfaces with slow rise and fall times mask poorly terminated boards. This is why sometimes cheap low speed JTAG interfaces work and high speed ones don’t.
Correct TCK Termination
To correctly terminate a board, place a 100R resistor to ground at the end of the TCK net on the circuit board. Track the TCK net as a 100R track to each device in turn with out any stubs etc.
If you buffer the TCK signal, remember to terminate the TCK signal at the input to the buffer. Also each output of the buffer will need termination as above.
Dealing with poorly terminated boards
XJLink2 helps you to run tests on poorly terminated boards in two ways:
1) XJLink2 enables variable source termination impedances to match your board.
2) Variable Slew rates.
Variable source termination impedance match enable the XJLink2 to better match the termination on you board so if a 220R resistor is fitted for instance then you can select 220R as the source impedance. If you have no termination fitted then there is a “none” option as well.
The variable Slew rates enable the rise and fall times to be adjusted to improve the signal quality of the TCK. The slower the Slew rate the better the signal quality will be but the lower the maximum TCK frequency will be as well.
By adjusting the Source termination impedance and the Slew rate, XJLink2 can provide high quality signals across long cables into poorly terminated systems. For example, we recommend only using 15cm of JTAG cable; we have however used XJLink2 with over 4metres of cable at 20MHz, which was greater than the devices on the board were rated at.