This post is to try to clarify what XJTAG understands by the term “differential termination”.
XJTAG has a special class of passive device (DIFF_TERM) to represent this type of termination, which was introduced into XJTAG in version 2.2, and we regularly see it in projects, especially when testing RAM or 1149.6 devices.
When you mark a resistor as a differential termination resistor (DIFF_TERM) you are telling XJTAG that it represents a termination resistor placed between two nets. This resistor is not so low in impedance that the nets are expected to always read the same value (that would be represented by a CONNECT resistor/link) but low enough that if one net is driven and the other is not, you will read the driven value on both nets. You are also telling XJTAG that it is acceptable to drive the two nets to opposite values in either Connection Test or XJEase tests (which XJTAG would not allow if the two nets were CONNECTed).
This connection type is useful in multiple scenarios:
- We often see situations such as the clock signal on DDR memory, where we have a differential signal driven by standard I/O pins on a JTAG-compliant device. The nets are often terminated by a value such as 100 Ω which is easily detectable by Connection Test. Marking the termination resistor as DIFF_TERM means that Connection Test will expect to detect a short-circuit between the pins (and will fail if the resistor is missing), but also means that XJEase can drive the +ve and -ve clock pins to opposite values during memory testing.
- In 1149.6 scenarios the high-speed nets involved usually have to be terminated, and DIFF_TERM gives a way to represent direct terminations between the +ve and -ve legs of differential signals.
- DIFF_TERM resistors cannot be used to represent centre-referenced terminations between differential nets.
- If the termination consists of multiple resistors in series (but with no reference voltage attached), classify one of them as DIFF_TERM and the other(s) as CONNECT devices.
[…] represents a simple termination resistor placed between two differential nets and is covered in a separate blog entry, whereas BIAS_TERM represents a termination to a reference voltage. BIAS_TERM was introduced into […]