Tips for setting up an XJLink-PF40 pin mapping

With the release of the XJLink-PF40 and XJTAG 4.1, setting up your pin mapping might have just got a bit more complicated. The XJLink-PF40 supports twice as many TAPs (8) and has twice as many I/O pins (40) as the XJLink2 so there can be more work involved in setup. Luckily, XJDeveloper 4.1 contains some [...]

Built-in Test Reset Sequences for devices with nTRST pins

XJTAG 4.1 can automatically generate test reset sequences for many more hardware designs than previous versions. Previously, if a JTAG device had an nTRST pin that needed resetting between tests, you had to manually create a sequence with a waveform like the following: […]

Multi-sourcing Device Configurations

New in version 4.1, XJTAG has support for multi-sourcing test device configurations. This post will explain how to define multiple possible configurations for your test devices. A follow-up post will compare XJTAG’s Variants, Revisions and Multi-sourcing features and explain which is best to use in different scenarios. […]

Optimised Scans

Optimised scans is a new feature added to XJTAG 4.0 and it provides a number of improvements aimed at increasing test speed. With Optimised Scans enabled, every JTAG TAP will scan data through at a separate frequency based on the capabilities of the JTAG devices in that TAP group. […]

2024-06-03T16:49:49+01:00By |Categories: Features, XJDeveloper|Tags: , |

Extending XJTAG’s Signal Integrity Error Analysis

Continuing from XJTAG 3.12’s Enhanced Signal Integrity Analysis feature (see here and here), XJTAG 3.13 brings more algorithms to help identify potential issues with the JTAG chain. This article describes more of the symptoms it can spot and their likely causes. […]

Improve your printed circuit board test, debug and programming processes using XJTAG’s powerful boundary scan test suite. It can speed up your design and development, as well as providing excellent test coverage in production.
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