We have recently seen Agilex BSDL files that cause XJDeveloper to emit errors looking like this: The cause of this is a mismatch of information. Within the BSDL file, in the Advanced I/O description (AIO) section, there is a section that describes the pins' AC capabilities for IEEE 1149.6 testing. In this section each AC-capable [...]
XJTAG 4.1 introduces enhancements to the ARM Serial Wire Debug (SWD) protocol to return protocol operation acknowledgement responses in XJEase. […]
With the release of the XJLink-PF40 and XJTAG 4.1, setting up your pin mapping might have just got a bit more complicated. The XJLink-PF40 supports twice as many TAPs (8) and has twice as many I/O pins (40) as the XJLink2 so there can be more work involved in setup. Luckily, XJDeveloper 4.1 contains some [...]
New in version 4.1, XJTAG has support for multi-sourcing test device configurations. This post will explain how to define multiple possible configurations for your test devices. A follow-up post will compare XJTAG’s Variants, Revisions and Multi-sourcing features and explain which is best to use in different scenarios. […]
Here is a summary of the additions to the XJEase library made recently in library version 183. Note: Some files in this library require an XJTAG software version of at least 3.10.6. […]
XJTAG 4.0 has significantly improved the user experience of creating and editing test reset sequences – the way in which JTAG devices are put into their JTAG mode. […]
XJTAG 3.12 expanded the capability of the Signal Integrity Analysis in XJTAG tools, adding the ability to suggest certain causes of error. This post continues from the previous post on this subject, and describes further errors that XJTAG tries to identify. […]
(This updates an older article due to the addition of the Excluded category in XJTAG 3.12) One of the questions we are commonly asked by new users, and also by users who have not used XJTAG for a while and are coming back to it, is about the differences between device categorisations in XJDeveloper. [...]
Historically we have provided three mechanisms for defining some form of constant or default values for a pin/net in XJDeveloper. These are BSDL compliance pins, bus disable values and constant pins, which allow you to define pins which XJTAG should keep in a constant state during automated testing, such as with Connection Test. However these [...]
With the introduction of External Hardware per Subchain in XJDeveloper v3.9 it is possible to write a test that powers up your board using your XJLink2 to directly control the IIC pins before the JTAG chain is operable. Following is an example of how to set up this test in your project: [...]