The JTAG standard contains definitions for various different types boundary scan cells, each of which have different capabilities, and these allow an IC vendor to accurately describe how the pins on their chips behave. But because not every eventuality can be foreseen the JTAG specification also allows IC vendors to create their own types of boundary scan cells. […]
(This article has now been replaced by an updated version, here.) […]
Recently one of our newer customers started on their first solo board setup. They had previously seen XJTAG demonstrated and had also had their initial board setup done by an XJTAG engineer. When they came to setting a board up for themselves they tried to follow the path that the XJTAG engineer had talked them through – […]
‘Dynamic Chains’ is a term we’ve coined to describe a test system that has the ability to drive more that 1 JTAG chain configuration. This may be possible if it has multiple chains driven by different TMS or TCK pins, or a single chain that has multiple JTAG device variations (for example using a Scan Bridge). Before v3.3, XJTAG projects could only represent a single static JTAG chain. With our new functionality, multiple JTAG chain variations can be defined, set up and run within a single XJTAG project in a single test run. […]
We recently had to support a customer who was unable to run XJTAG 3.1 on an older PC. It turned out that the processor in the PC in question did not support SSE2 instructions. During the development of v3.1 we upgraded the compiler we use to build XJTAG and it now uses these instructions to speed up execution. SSE2 instructions were introduced with the Pentium 4 in 2001 and were supported in AMD processors with their Opteron and Athlon 64 processors from 2003 onwards.