Automatic suggestion of JTAG chains
To help get your tests up and running more quickly and easily, version 2.7 of XJDeveloper has a new feature which can make suggestions for the JTAG chains in your project. […]
How can Checkchain pass but Connection test report “broken chain”?
This is a common question during the development of a test system. The problem generally occurs when a board is first run, and stems from a slight misunderstanding of what Checkchain is designed to do. This article therefore attempts to explain the difference between the Checkchain function and all other tests, in order to explain [...]
Create your own links to Layout Viewer from XJEase
From version 2.6.2 onwards XJEase supports the printing of device, pin and net links which launch and get highlighted in Layout Viewer from XJRunner and XJDeveloper (provided there is an ODB++ netlist available for the board). […]
Layout Viewer
If your project uses an ODB++ netlist, then you can take advantage of the Layout Viewer in both XJDeveloper and XJRunner. Layout Viewer uses the layout information in the netlist to allow you to visualise the physical location of components, pins and nets on a board. This is especially useful for visualising errors from the [...]
Device Library
Version 2.6 of XJDeveloper has two exciting new features that make developing your projects easier – a library of definitions for devices and a “suggest categorisation” feature. […]
XJTAG Logic Library
From version 2.4 XJDeveloper and XJRunner support logic devices. A library of definitions for common logic devices is shipped with XJDeveloper. This post details this feature. […]
Categorising Devices as Logic in XJDeveloper
This post outlines how to categorise a device as a logic device in XJDeveloper and explains some of the useful features. […]
Design for Test Analysis in XJDeveloper 2.4 – Part 2
This post introduces the new DFT reports which are generated from the DFT analysis data. This is a feature introduced in XJTAG version 2.4. […]
Clearing Altera Cyclone III Devices
In the XJTAG application note “Working with configured Xilinx and Altera devices” the point is made that the way to get the best test coverage is to test with blank devices. Blanking a device has its own challenges – […]
Design for Test Analysis in XJDeveloper 2.4 – Part 1
The DFT Analysis screen in XJTAG version 2.4 has been completely redesigned to allow you to assess the test coverage of your circuit design more easily and in a more efficient way. This post highlights the most important new features. […]