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Custom cells in BSDL files

The JTAG standard contains definitions for various different types boundary scan cells, each of which have different capabilities, and these allow an IC vendor to accurately describe how the pins on their chips behave. But because not every eventuality can be foreseen the JTAG specification also allows IC vendors to create their own types of boundary scan cells.   […]

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Categorising devices: Ignore, Unfitted, or Uncategorised?

One of the questions we are commonly asked by new users, but also by users who have not used XJTAG for a while and are coming back to it, is about the differences between device categorisations in XJDeveloper. […]

Testing XJLink hardware

We understand that sometimes (for your own sanity if nothing else) you need to test that your test equipment is working. For this reason, it is possible to run a health-check on XJLink2 hardware (and XJLink2-based hardware) using the self-test feature available in the XJLink Manager. The self test can be run with or without a loopback connector but should never be run with the XJLink connected to test hardware. […]

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New XJEase library available

Today (31 Mar 2016) we have released a major update to the XJTAG XJEase library.  The new library will be installed if you update to version 3.4.5 of XJTAG which is also released today. […]

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Debugging Connection Test – part 1 (Updated)

This post is an update to the original “Debugging Connection Test (part 1)” post – over time several features in XJTAG have changed considerably and may be hard to find by following my original post. […]

Why categorise resistors, inductors, links and fuses?

Recently one of our newer customers started on their first solo board setup. They had previously seen XJTAG demonstrated and had also had their initial board setup done by an XJTAG engineer. When they came to setting a board up for themselves they tried to follow the path that the XJTAG engineer had talked them through – […]

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Categorising Transistors in XJDeveloper

Transistors are one of the things we get asked about quite a bit: “How should I categorise the transistors in my project?” […]

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Windows XP support

Windows XP was released in October 2001 and has been one of Microsoft’s most successful operating systems. […]

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Introducing Dynamic Chains

‘Dynamic Chains’ is a term we’ve coined to describe a test system that has the ability to drive more that 1 JTAG chain configuration. This may be possible if it has multiple chains driven by different TMS or TCK pins, or a single chain that has multiple JTAG device variations (for example using a Scan Bridge). Before v3.3, XJTAG projects could only represent a single static JTAG chain. With our new functionality, multiple JTAG chain variations can be defined, set up and run within a single XJTAG project in a single test run. […]

Minimum processor requirements for XJTAG

We recently had to support a customer who was unable to run XJTAG 3.1 on an older PC. It turned out that the processor in the PC in question did not support SSE2 instructions. During the development of v3.1 we upgraded the compiler we use to build XJTAG and it now uses these instructions to speed up execution. SSE2 instructions were introduced with the Pentium 4 in 2001 and were supported in AMD processors with their Opteron and Athlon 64 processors from 2003 onwards.

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