When using JTAG with a Device Under Test (DUT) connected to a bed-of-nails test fixture, often little attention is paid to the way the JTAG signals are wired. This article (published in SMT magazine last year) gives a helpful explanation of why it is important to get this right, and gives tips for best practice.
We recently had to support a customer who was unable to run XJTAG 3.1 on an older PC. It turned out that the processor in the PC in question did not support SSE2 instructions. During the development of v3.1 we upgraded the compiler we use to build XJTAG and it now uses these instructions to speed up execution. SSE2 instructions were introduced with the Pentium 4 in 2001 and were supported in AMD processors with their Opteron and Athlon 64 processors from 2003 onwards.
A new XJRunner Integration .NET API was released in XJTAG 2.6. This came with a new set of LabVIEW examples detailing how the API could be used within the LabVIEW environment. These examples have been added to since that release. […]
We have had several customers having problems exporting ODB++ jobs from PADS, where all the net information is lost. In the ODB++ Export dialog, ensure that “Neutralize nets” is unchecked. […]
One of the many netlist formats that XJTAG supports is EDIF 2, an open data exchange format that is widely supported. EDIF stores both netlist and schematic data, but XJTAG only uses the netlist data. It often seems like the obvious choice of format to export from your CAD tool to use in XJTAG. However, there are a number of problems that we have come across with EDIF netlists: […]
We asked one of the guys in-house who works with XJDeveloper most of the time to give some tips from his experience of setting up projects, and here is what he came up with: […]
Texas Instruments’ OMAP processors are becoming more and more popular. We have seen quite a few come through the office recently. The good news is that the OMAP processors do support boundary scan testing. […]